Jiun Kai Beh

Solutions Architect with deep knowledge in Signal Integrity and Small Form Factor platform architecture in the Intel IOTG-RBHE Product & Technology team. He leads the Intel Smart Display Module (SDM) architecture, specification, and reference design development which supports 8K and 5G to expand SDM portfolio and market adoption.

Prior to joining IOTG, Jiun Kai was a Platform Architect within Intel IPG responsible for Hard-IP Validation Boards architecture definition and board development, including LPDDR4x, PCIE Gen5, Ethernet 112Gbps and Display interfaces. His experiences also include working as Package Electrical & Signal Integrity Engineer for High Speed I/O in Intel CCG. He developed new electrical modeling methodologies and conceptualized new signal waveform post-processing tools, which is adopted for SI analysis across multiple Intel groups.   Jiun Kai has published 17 technical papers in IP.com and IEEE conferences.